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publication release date: may 17, 2005 - i - revision 1.0 winbond integrated media reader w83l518d datasheet
w83l518d - ii - table of contents- 1. general description ......................................................................................................... 1 2. functions ............................................................................................................................... 1 2.1 general ............................................................................................................................. 1 2.2 smart card interface ........................................................................................................ 1 2.3 memory stick interface ..................................................................................................... 2 2.4 sd memory card interface .............................................................................................. 2 2.5 package ........................................................................................................................... 2 3. pin configuration for w83l518d ................................................................................... 3 4. pin description ..................................................................................................................... 4 4.1 bus interface .................................................................................................................... 4 4.2 smart card interface pins ................................................................................................ 5 4.3 memory stick interface/sd memory interface pins ......................................................... 6 4.4 general-purpose i/o pins ................................................................................................ 7 4.5 crystal and power pins .................................................................................................... 7 5. general-purpose i/o ports (gpio) ................................................................................ 8 6. configuration register .................................................................................................. 9 6.1 plug and play configuration ............................................................................................. 9 6.2 compatible pnp ............................................................................................................. 10 6.2.1 extended function register ........................................................................................... 10 6.2.2 extended functions enable register (efer) ................................................................. 10 6.2.3 extended function index register (efir), extended function data register (efdr) ... 11 6.3 configuration sequence ................................................................................................. 11 6.3.1 software programming example ..................................................................................... 11 6.4 global registers ............................................................................................................. 12 6.5 logical device 0 (smart card interface) ........................................................................ 14 6.6 logical device 1 (memory stick interface) .................................................................... 15 6.7 logical device 2 (gpio) ................................................................................................ 16 6.8 logical device 3 (sd memory interface) ....................................................................... 17 7. ordering instruction ..................................................................................................... 18 8. how to read the top marking ...................................................................................... 19 9. package drawing and dimensions .............................................................................. 20 10. the w83l518d schematic .................................................................................................. 21 11. revision history ................................................................................................................ 23
w83l518d publication release date: may 17, 2005 - 1 - revision 1.0 1. general description w83l518d is winbond's innovative solution to a new class of storage devices for ia noetebook, desktop pc and pc system-related products. it incor porates a security application: smart card interface and two most promising compact storage interfaces: memory stick interface, and sd memory card/multimedia card interface in it era. to cater boundless it implementation possibilities, w83l518d can be configured to interface with host through lpc bus. base on the lpc interface, one smart card interface port and two flash memory interfaces - memory stick and sd memory ports are provided. the kind of versatility allows user to design very cost-effective products in a very flexible way. the whole chip of w83l518d operates at voltage level of 3.3 v except smart card interface port's i/o pins that are at 5 v to be compatible with main stream smart card implementations. advanced power management feature further optimizes power consum ption whether in operation or in power down mode. w83l518d comes as a 48-pin lqfp streamline pa ckage. combining with powerful functions, effective power management, and versatile configurab ility, this integrated media reader offers a perfect approach for design of storage device of it products. the trademarks and intellectual property rights of memory stick belong to sony corporation. information check: http://www.memorystick.org/ the trademarks and intellectual property rights of secure digital belong to sd group. information check: http://www.sdcard.org/ 2. functions 2.1 general ? lpc bus is compliant with lpc spec. 1.01 ? lpc bus supports ldrq# (lpc dma), serirq (serial irq) ? programmable configuration settings ? 48 mhz crystal inputs ? pciclk of 33 mhz is needed for lpc bus configuration 2.2 smart card interface ? iso-7816 compliant ? pc/sc t=0, t=1 compliant ? 16-byte transmitter fifo and 16-byte receiver fifo ? fifo threshold interrupt to optimize system performance ? programmable transmission clock frequency ? versatile baud rate configuration ? uart-like register file structure ? general-purpose c4, c8 channels
w83l518d - 2 - 2.3 memory stick interface ? memory stick standard format specifications ver. 1.3 compliant ? support memorystick pro (serial mode) ? support interrupt polling transmission ? support fifo threshold interrupt to optimize system performance ? automatic clock halt to prevent underrun/overrun ? 16 mhz interface clock 2.4 sd memory card interface ? sd memory card specifications: part 1 physical layer specification version 1.0 compliant ? support multimedia card ? support interrupt polling transmission ? support fifo threshold interrupt to leverage system performance ? 24 mhz interface clock 2.5 package ? 48-pin lqfp
w83l518d publication release date: may 11, 2005 - 3 - revision 1.0 3. pin configuration for w83l518d w83l518d pcicl k ldrq # lframe # reset # pme # vss gp17 gp16 gp15 gp14 gp13 gp12 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 sdpwr#/gp21 sdled/gp20 scc4 scc8 msled mspwr# vss msclk ms1 ms2 ms3 ms4 sdclk /gp22 sd1 /gp23 sd2 /gp24 vdd3v sd3 /gp25 sd4 /gp26 sd5 /gp27 lad3 lad2 lad1 lad0 serirq ms5 xin xout scrst# scio scclk scpsnt scpw r# scled vdd gp10 gp11 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48
w83l518d - 4 - 4. pin description note: in t - 5v ttl level input pin in tp3 - 3.3v ttl level input pin in ts - 5v ttl level schmitt-trigger input pin in tsp3 - 3.3v ttl level schmitt-trigger input pin i/o 12t - 5v ttl level bi-directional pi n with 12 ma drive-sink capability i/o 24t - 5v ttl level bi-directional pi n with 24 ma drive-sink capability i/o 16tp3 - 3.3v ttl level bi-directional pin with 16 ma drive-sink capability o 2 - 5v output pin with 2 ma drive-sink capability o 12 - 5v output pin with 12 ma drive-sink capability o 16p3 - 3.3v output pin with 16 ma drive-sink capability od 12p3 - 3.3v open-drain output pin with 12 ma sink capability. 4.1 bus interface symbol pin i/o function pme# 5 od 12p3 active-low pme event. reset# 4 in tsp3 active-low system reset signal. lframe# 3 in tsp3 active-low signal indicates start of a new lpc frame or termination of a premature frame. ldrq# 2 o 16p3 encoded dma request signal. pciclk 1 in tsp3 pci clock input of 33 mhz. serirq 48 i/o 16tp3 serial irq input/output. lad0 47 i/o 16tp3 this signal combining with other ladx signals communicate address, control, and data inform ation over the lpc bus between a host and a peripheral. lad1 46 i/o 16tp3 this signal combining with other ladx signals communicate address, control, and data inform ation over the lpc bus between a host and a peripheral. lad2 45 i/o 16tp3 this signal combining with other ladx signals communicate address, control, and data inform ation over the lpc bus between a host and a peripheral. lad3 44 i/o 16tp3 this signal combining with other ladx signals communicate address, control, and data inform ation over the lpc bus between a host and peripherals.
w83l518d publication release date: may 11, 2005 - 5 - revision 1.0 4.2 smart card interface pins symbol pin i/o function scc4 34 i/o 16tp3 smart card interface general purpose i/o channel for connector pin c4 on a card. scc8 33 i/o 16tp3 smart card interface general purpose i/o channel for connector pin c8 on a card. scled 16 o 24 this pin outputs an oscillating clock signal of various frequencies depending on traffic of primary smart card interface. scpwr# 17 o 24 smart card interface power control signal. scpsnt 18 in ts smart card interface card pr esent detection schmitt-trigger input. scclk 19 o 2 smart card interface clock output. scio 20 i/o 12t smart card interface data i/o channel. scrst# 21 o 12 smart card interface reset output.
w83l518d - 6 - 4.3 memory stick interface/sd memory interface pins symbol pin i/o function msled 32 o 16p3 memory stick function - this pin outputs an oscillating clock signal of various frequencies depending on traffic of the memory stick interface. mspwr# 31 o 16p3 memory stick function - this pin is power control signal for the memory stick interface. msclk 29 o 16p3 memory stick function - this pin is sclk for the memory stick interface. ms1 28 o 16p3 memory stick interface pin. ms2 27 i/o 16tp3 memory stick interface pin. ms3 26 --- memory stick interface pin. ms4 25 in tsp3 memory stick interface pin. ms5 24 --- memory stick interface pin. sd5 43 i/o 16tp3 sd interface pin. sd interface pin. 42 i/o 16tp3 sd interface pin. sd interface pin. 41 i/o 16tp3 sd interface pin. sd interface pin. 39 i/o 16tp3 sd interface pin. sd interface pin. 38 i/o 16tp3 sd interface pin. sdclk 37 o 16p3 sd function - this pin is clk for the sd memory card interface. sdpwr# 36 o 16p3 sd function - this pin is power control signal for the sd memory card interface. sdled 35 o 16p3 sd function - this pin outputs an oscillating clock signal of various frequencies depending on traffic of the sd memory card interface. card_detect 13 in t function as an alternative card detection input for the sd memory interface.
w83l518d publication release date: may 11, 2005 - 7 - revision 1.0 4.4 general-purpose i/o pins symbol pin i/o function gp17 7 i/o 12t general-purpose i/o port 17. gp16 8 i/o 12t general-purpose i/o port 16. gp15 9 i/o 12t general-purpose i/o port 15. gp14 10 i/o 12t general-purpose i/o port 14. gp13 11 i/o 12t general-purpose i/o port 13. gp12 12 i/o 12t general-purpose i/o port 12. gp11 ex_cd 13 i/o 12t general-purpose i/o port 11. external card detedtion pin. the detectable level can be set on bit 2 of cr f0 on logical device 3. gp10 phefras 14 i/o 12t in t general-purpose i/o port 10. this pin also functions as a power-on setting pin whose value is latched on the rising edge of reset# (pin 4) to select configuration ports as 2eh/2fh (phefras = 1) or 4eh/4fh (phefras = 0). it determines the default value of cr26 bit 6 (hefras). 4.5 crystal and power pins symbol pin function xout, xin 22, 23 connected to a 48 mhz crystal and function as the working clock for all the media reader interfaces. vdd3v 40 +3.3v power supply for host interf ace, memory stick/sd memory interfaces, and internal core. vdd 15 +5v power supply for smart card interface i/o pins. vss 6, 30 ground.
w83l518d - 8 - 5. general-purpose i/o ports (gpio) w83l518d supports one group of dedicated general-pur pose i/o ports and a multi-functional gpio group, which share the same pines with the sd interface sockets. there are cases when only one socket is needed in a system and pins for the other unused socket are wasted. to provide the most cost-effective solution, w83l518d could be configur ed to transform these pins into general-purpose i/o ports. the first group (gp10 ~ 17) is configured through t he configuration registers crf0 ~ crf2 in logical device 2 and the other group (gp20 ~27) through crf3 ~ f5. users can configure each individual port to be an input or output port by programming respec tive bit in direction register (crf0/crf3: 0 = output, 1 = input). invert port value by setting in version register (crf2/crf5: 0 = non-inverse, 1 = inverse). port value is read/written through data register (crf1/crf4). table 5.1 and 5.2 illustrate gpio's assignment. to further facilitate system design, w83l518d allows direct accesses to data register and direction register through i/o ports, whose base address is programmable at cr 60, 61 in logical device 2. detailed configuration is described in logical device 2 of section 6: configuration register. gp10 (pin 14) also functions as a power-on setti ng pin whose value is latched on the rising edge of reset# (pin 4) to select configuation port addresse s. therefore, gp10 is a push-pull i/o port unlike the other gpio ports, which are open-drained i/o s to support this power-on setting feature. gp11 (pin 13) could function as a card detection input if selected by sdi to support some mmc cards, which don't offer card detecti on feature through data3 pin. table 5.1 direction bit 0 = output 1 = input inversion bit 0 = non inverse 1 = inverse i/o operation 0 0 basic non-inverting output 0 1 basic inverting output 1 0 basic non-inverting input 1 1 basic inverting input
w83l518d publication release date: may 11, 2005 - 9 - revision 1.0 table 5.2 gpio port data register register bit assignment gp i/o port bit 0 gp10 bit 1 gp11 bit 2 gp12 bit 3 gp13 bit 4 gp14 bit 5 gp15 bit 6 gp16 gp1 bit 7 gp17 bit 0 gp20 bit 1 gp21 bit 2 gp22 bit 3 gp23 bit 4 gp24 bit 5 gp25 bit 6 gp26 gp2 bit 7 gp27 6. configuration register 6.1 plug and play configuration w83l518d/w83l519d implement compatible pnp protoc ol to access configuration registers for setting up different types of configurations. ther e are four logical devices (logical device 0 to logical device 3) in w83l518d/w83l519d which corre spond to four major functions: smart card interface (logical device 0), memory stick interfac e (logical device 1), gpio (logical device 2) and sd memory interface (logical device 3). each logical device has its own configuration registers (cr30 and above). host can access those registers by writing an appropriate logical device number into logical device select register at cr07 first.
w83l518d - 10 - one set per logical device logical device select 07 h 30 h 40 h feh 3f h logical device control global registers logical device configuration 6.2 compatible pnp 6.2.1 extended function register w83l518d/w83l519d provide two methods to enter extended function mode (compatible pnp) and access configuration registers dependent on value of hefras (bit 6 of cr26. the corresponding power-on setting pin is pin 14) as follows: hefras address and value 0 write 83h to i/o address 2eh twice 1 write 83h to i/o address 4eh twice in compatible pnp, a specific value (83h) mu st be written twice to the extended function enable register (efer at i/o address 2eh or 4eh). secondly, an index va lue (02h, 07h-ffh) must be written to the extended function index regi ster (efir, i/o address at 2eh or 4eh which is the same as efer) to identify which configuration register is to be accessed. user can then access the addressed configuration register through t he extended function data register (efdr, i/o address at 2fh or 4fh). after programming of the configuration register is completed, another specific value (0aah) should be written to efer to leave extended function m ode to prevent inadvertent accesses to those configuration registers. user may write a "1" to bit 5 of cr26 (lockreg) to prevent configuration registers from accidental accesses. 6.2.2 extended functions enable register (efer) after a power-on reset, w83l518d/w83l519d enters the default operation mode. a specific value must be programmed into the extended function enabl e register (efer) so that configuration registers can be accessed. on a pc/at system, its i/o address is 2eh or 4eh (as described in previous section).
w83l518d publication release date: may 11, 2005 - 11 - revision 1.0 6.2.3 extended function index register (efir), extended function data register (efdr) after entering extended function mode, extended func tion index register (e fir) must be written with an index value (02h, 07h-feh) to specify whic h configuration register is to be accessed through extended function data register (efdr). efir is a write-only register at i/o address 2eh or 4eh (as described in section 6.2.1) on a pc/at system and efdr is a read/wr ite register at i/o address 2fh or 4fh. 6.3 configuration sequence to program configuration registers, specific configuration sequence must be followed: (1) write 83h to efer twice to enter extended function mode. (2) select logical device select register by writing 07h to efir. (3) select logical device by writing a value to efdr. (4) select control/configuration regi ster by writing its index to efir. (5) access selected control/confi guration register through efdr. (6) repeat step 4 ~ 5 as needed. (7) leave extended function mode by writing aah to efer. step 2 and step 3 are not necessary for acce ssing global register (index 00h to 2fh). 6.3.1 software programming example the following example is written in intel 8086 assembly language. efer and efir are assumed to be at 2eh, and efdr is at 2fh. use 4eh/4fh inst ead of 2eh/2fh if hefras (bit 6 of cr26) is set. ;----------------------------------------------------------------------------------- ; enter extended function mode, interruptible double-write | ;----------------------------------------------------------------------------------- mov dx, 2eh mov al, 83h out dx, al out dx, al ;----------------------------------------------------------------------------- ; configure logical device 1, configuration register crf0 | ;----------------------------------------------------------------------------- mov dx, 2eh mov al, 07h out dx, al ; point to logical device number reg. mov dx, 2fh mov al, 01h out dx, al ; select logical device 1
w83l518d - 12 - ; mov dx, 2eh mov al, f0h out dx, al ; select crf0 mov dx, 2fh mov al, 3ch out dx, al ; update crf0 with value 3ch ;------------------------------------------ ; exit extended function mode | ;------------------------------------------ mov dx, 2eh mov al, aah out dx, al 6.4 global registers cr02 (default 00h, write only) bit [7:1]: reserved. bit 0: swrst = 0 normal operation. = 1 software reset. cr07 (default 00h) bit [7:0]: logical device number. cr20 (read only) bit [7:0]: device id number (higher byte). = 71h cr21 (read only) bit [7:0]: device id number (lower byte) = 1xh (for w83l518d) = 2xh (for w83l519d) x: revision number cr22 (default 80h) bit 7: scpwd = 0 power down smart card interface. = 1 no power down.
w83l518d publication release date: may 11, 2005 - 13 - revision 1.0 bit 6: mspwd = 0 power down memory stick interface. = 1 no power down. bit 5: sdpwd = 0 power down sd memory card interface. = 1 no power down. bit [4:0]: reserved. cr23 (default 00h) bit 7: pme_en. power management event enable bit. = 0 pme_l function is disabled. = 1 enable to issue a low pulse on pme_l when a power management event occurs. bit 6: mspme_en. memory stick interface power management event enable bit. = 0 memory stick interface power management event is disabled. = 1 enable memory stick interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit 5: sdpme_en. sd memory card interface power management event enable bit. = 0 sd memory card interface pow er management event is disabled. = 1 enable sd memory card interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit 4: scpme_en. smart card in terface power management event enable bit. = 0 smart card interface power management event is disabled. = 1 enable smart card interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit [3:0]: reserved. cr24 (default 00h) bit 7: reserved. bit 6: mspme_sts. memory stick in terface power management event status bit. = 0 no memory stick interfac e power management event occurs. = 1 memory stick interface power management event occurs. bit 5: sdpme_sts. sd memory card interface power management event status bit. = 0 no sd memory card interface power management event occurs. = 1 sd memory card interface power management event occurs. bit 4: scpme_sts. smart card inte rface power management event status bit. = 0 no smart card interface power management event occurs. = 1 no smart card interface power management event occurs. bit [3:0]: reserved.
w83l518d - 14 - cr26 (default 40h) bit 7: reserved bit 6: hefras, extended function register address select. the corresponding power-on setting pin is gp10 (phefras, pin 14). t he hefras is defaulted to "1" if phefras is "0" and is defaulted to "0" if phefras is "1". = 0 extended function registers are at 2eh/2fh. = 1 extended function registers are at 4eh/4fh. bit 5: lockreg = 0 enable accesses of configuration registers. = 1 disable accesses of configuration registers. bit [4:0]: reserved cr29 (default 00h, only valid in w83l518d) bit 7: multi-function selection bit for pin 7 ~ 14 = 0 pin 7 ~ 14 function as smart card interface socket b. = 1 pin 7 ~ 14 function as gpio1. bit 6: multi-function selection bit for pin 35 ~ 43 = 0 pin 35 ~ 43 function as msi/sdi socket b. = 1 pin 35 ~ 43 function as gpio2. bit 5: multi-function selection bit for pin 32 ~ 31 & pin 29 ~ 24. = 0 pin 32 ~ 31 and pin 29 ~ 24 function as msa (ms interface card a). = 1 pin 32 ~ 31 and pin 29 ~ 24 function as sda (sd interface card a). bit 4: multi-function selection bit for pin 43 ~ 41 & pin 39 ~ 35. = 0 pin 43 ~ 41 & pin 39 ~ 35 function as msb (ms interface card b). = 1 pin 43 ~ 41 & pin 39 ~ 35 function as sdb (ms interface card b). bit [3:0]: reserved. 6.5 logical device 0 (smart card interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0 logical device is inactive. = 1 activates the logical device. cr60, cr61 (default 0x00, 0x00) these two registers select smart card base address [0x100:0xfff] on 8-byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for smart card interface.
w83l518d publication release date: may 11, 2005 - 15 - revision 1.0 crf0 (default 0x00) bit 7: irq sharing control bit. = 0 no irq sharing. = 1 irq sharing. bit 0: scpsnt_pol (smart card pres ent polarity). scpsnt polarity bit. = 0 scpsnt is active high. = 1 scpsnt is active low. 6.6 logical device 1 (memory stick interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0: logical device is inactive. = 1: activates the logical device. cr60, cr61 (default 0x00, 0x00) these two registers select msi base address [0x100:0xfff] on 8-byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for msi. cr74 (default 0x04) bit [7:4]: reserved. bit [3:0]: these bits select drq resource for msi. crf0 (default 0x00) bit [7:5]: reserved. bit 4: irq polarity control bit by level mode. = 0: irq is active high. = 1: irq is active low. bit 3: irq polarity control bit by pulse mode. = 0: irq is active low. = 1: irq is active high. bit 2: irq sharing control bit. = 0: no irq sharing. = 1: irq sharing.
w83l518d - 16 - bit 1: ms4 output polarity control bit. 0: ms4 output low. 1: ms4 output high. bit 0: ms4 output enable bit. 0: ms4 output disable. 1: ms4 output enable. 6.7 logical device 2 (gpio) cr30 (default 00h) bit [7:3]: reserved. bit 2: individual disable/enable bit for gpio2. = 0 gpio2 is disabled if bit 0 is also "0". = 1 gpio2 is enabled. bit 1: individual disable/enable bit for gpio1. = 0 gpio1 is disabled if bit 0 is also "0". = 1 gpio1 is enabled. bit 0: logical device disable/enable bit. = 0 gpio1 and gpio2 are disabled/enabled dependent on bit 1 and 2 respectively. = 1 activates gpio1 and gpio2. cr60, cr61 (both default 00h) base address configuration registers: programmable at addresses from 0100h to 0ff8h on 4-byte boundary. base address + 0 and base address + 1 ar e for gpio1 as direction register and data register respectively while base address + 2 and base address + 3 are for gpio2 as direction register and data register respectively. crf0 (gp10 ~ gp17 direction register. default ffh) when set to "1", respective gpio port is programmed as an input port. when set to a "0", respective gpio port is programmed as an output port. crf1 (gp10 ~ gp17 data register. default 00h) if a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. if a port is programmed to be an i nput port, its respective bit reflects what is on respective pin. crf2 (gp10 ~ gp17 inversion register. default 00h) when set to "1", respective incoming/outgoing port va lue is inverted. when set to "0", respective incoming/outgoing port value is the same as in data register. crf3 (gp20 ~ gp27 direction register. default ffh) when set to "1", respective gpio port is programmed as an input port. when set to a "0", respective gpio port is programmed as an output port.
w83l518d publication release date: may 11, 2005 - 17 - revision 1.0 crf4 (gp20 ~ gp27 data register. default 00h) if a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. if a port is programmed to be an i nput port, its respective bit reflects what is on respective pin. crf5 (gp20 ~ gp27 inversion register. default 00h) when set to "1", respective incoming/outgoing port va lue is inverted. when set to "0", respective incoming/outgoing port value is the same as in data register. 6.8 logical device 3 (sd memory interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0 logical device is inactive. = 1 activates the logical device. cr60, cr61 (default 0x00, 0x00) these two registers select sd card interf ace base address [0x100:0xfff] on 8-byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for sd interface. cr74 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select drq resource for sd interface. crf0 (default 0x01) bit [7:6]: reserved. bit 5: set the output value of t he data3 pin when bit4 is setted 1. = 0 the data3 pin will output low. = 1 the data3 pin will output high. bit 4: set the data3 (ms1 or msb1) pin to output pin. = 0 set the data3 pin to bi-direction pin. = 1 set the data3 pin to output pin. bit 3: reserved. bit 2: select the pole of the gp11 card-detect pin. = 0 when detecting the low signal indicate the card is inserted and high signal indicate the card is extracted. = 1 when detecting the high signal incicate the card is inserted and low signal indicate the card is extracted.
w83l518d - 18 - bit 1: select gp11 pin to detect card. = 0 don?t use the gp11 pin to detect card. = 1 use the gp11 (scbpwr_l) pin to detect card. bit 0: select data3 pin to detect card. = 0 don?t use the data3 (ms1 or msb1) to detect card. = 1 use the data3 (ms1 or msb1) pin to detect card. crf1 (default 0x01) bit [7:4]: reserved. bit 3: set the irq pole for level mode. = 0 the irq is active high. = 1 the irq is active low. bit 2: set the irq pole for pulse mode. = 0 the irq is active low. = 1 the irq is active high. bit 1: set the irq to level mode or pulse mode. = 0 the irq is level mode. = 1 the irq is pulse mode. bit 0: use debounce function for card-detect circuit. = 0 no debouunce. = 1 use debounce function. 7. ordering instruction part no. package remarks w83l518d 48-pin lqfp
w83l518d publication release date: may 11, 2005 - 19 - revision 1.0 8. how to read the top marking 1st line: winbond logo and the smart@io trademark s mart@ io w83l518d 201gbsb 2nd line: the chip part number. 3rd line: tracking code 201 g b sb 201 : packages made in ' 02 , week 01 g : assembly house id; o means ose, g means gr, ? bsb : ic revision
w83l518d - 20 - 9. package drawing and dimensions package- 48-pin lqfp y seating plane d e e b a2 a1 a 1 12 48 d h e h l1 l c t controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
w83l518d publication release date: may 17, 2005 - 21 - revision 1.0 10. the w83l518d schematic 5vcc sd3 mspwctl# msled sd[5:1] sd4 lad2 inbond winbond electronics corp. sd2 hefras rp1 8p4r-4.7k 1 3 5 7 2 4 6 8 sc_vcc y1 48mhz r14 10 1 2 c9 0.1u 1 2 d3 led msclk sd3 c6 4.7u 1 2 5vcc pme# lad1 power-on strapping for 2e/2f (config. port) sd_3vcc sd_3vcc 3vcc 3vcc sd_3vcc xout q5 npn sc_vcc r24 330 r22 330 sdpwctl# d5 led the lc resonance circuit is used to filter base frequency of 3rd overtone crystal. scc8 q4 mosfet p scled scled xin r13 1m 1 2 sd2 r21 10k 1 2 sdpwctl# pciclk ms[5:1] r15 10 1 2 ms4 c5 10p r18 33 1 2 scpsnt sd4 r17 10 1 2 r25 1k 1 2 wr_pt c4 10p r16 4.7k 1 2 c7 0.1u 1 2 r30 1k r28 10k scclk r23 33 1 2 sc_vcc r31 4.7k 1 2 serirq ms1 r19 4.7k 1 2 soft start to protect mosfet(optional) w83l518d recommend circuit 0.6 b 12 wednesday, october 02, 2002 title size document number rev date: sheet of ex_cd r35 4.7k 1 2 without sd led function r32 330 1 2 q3 mosfet p u1 w83l518d_sb (lpc) 11 10 9 6 8 7 5 4 45 3 2 12 40 42 1 48 47 46 44 43 39 41 13 14 15 16 17 18 19 20 22 23 24 21 25 30 26 27 28 29 34 36 31 32 33 35 38 37 gp13 gp14 gp15 vss gp16 gp17 pme# lreset# lad2 lframe# ldrq# gp12 vdd3v sd4 pciclk serirq lad0 lad1 lad3 sd5 sd2 sd3 gp11/ex_cd gp10/hefras vdd scled scpwctl# scpsnt scclk scio xout xin ms5 scrst# ms4 vss ms3 ms2 ms1 msclk scc4 sdpwctl# mspwctl# msled scc8 sdled sd1 sdclk r34 1k 1 2 scc4 xin d6 led sc_vcc sd5 3vcc 3vcc sdclk lad3 5vcc scio scrst# r27 20k 1 2 scio sd1 ex_cd sd socket (1) circuit. j2 sd_socket 1 2 3 4 5 6 7 8 9 11 10 sd1 sd2 vss1 vdd sdclk vss2 sd3 sd4 sd5 wr_pt ex_cd# sdled sc_vcc 5vcc sdled 3vcc scpsnt scpwctl# l1 2.2uh 1 2 scclk sc read/write led soft start to protect mosfet(optional) 3vcc scc8 r26 4.7k sdclk sd5 lad0 hefras + c8 1u sc socket (1) circuit. j3 sc_socket 1 2 3 4 5 6 7 8 9 10 c1 c2 c3 c4 c5 c6 c7 c8 s1 s2 r29 1m sd_3vcc ms5 + c10 1u r20 330 1 2 ms3 u2 48mhz 7 8 14 gnd out vcc q6 npn lframe# pcirst# lad[3:0] scrst# d4 led sdled ms2 xout scpwctl# r12 10 1 2 sd1 scc4 s1 sw spdt 2 1 3 thew83l518dschematic
w83l518d - 22 - extension connectors (r_jp1) (ver 0.5 --> ver 0.6) scled (2)modified pulled-high resistor for write_protect detection from 500 ohm to 4.7k ohm. jp1,2: 1x10;pitch(2.0mm) (1)modified note 3 . sdclk mspwctl# ms1 r_jp1,2: 1x10 ; 2.0 mm(pitch) sd5 3vcc msclk scpsnt note 2: sd1 ms3 sd1 note 3: scrst# (3)added configuration port selection pin(gp10/hefras) by power-on strapping. sdled scpwctl# 3vcc ms2 r8 1m 1 2 pin 6 10 r9 1m 1 2 jp3: 2x5 ;pitch(2.54mm) scrst# r10 1m 1 2 (1)added circuit(gp10/ex-cd)to implement to sockets with external card detection pin. ms5 r1 330 1 2 ms_3vcc r6 1k 1 2 q1 mosfet p 5vcc inbond winbond electronics corp. scc4 jp1 1 2 3 4 5 6 7 8 9 10 (r_j1) sd5 if jp1,2,3,4 are designed for winbond recommended reader please meet following connector spec. (ver 0.2 --> ver 0.3) d1 led msclk r4 330 5 sd1 ms4 (r_jp2) note 5: msclk r3 4.7k the reset# should be connected with a low asserted signal like pcirst# on pci bus or lrest#on lpc bus(active low) (ver 0.1 --> ver 0.2) ms read/write led if any of sc or ms/sd function isn't intened to use, signals like scpsnt/sd1/ms1 should be tied to a pull-down resistor and sd4/ms4 should be tied to a pull-high resistors. (recommended: 1m ohm ) r7 1m 1 2 jp3 header 5x2 16 27 38 49 510 winbond recommended reader board sd4 scpwctl# ms5 sd4 scio 3vcc mspwctl# scc8 note 1: ms2 scclk sd3 (1)added power-on strapping circuit of different configuration port.(2e/2f) sdpwctl# r_j1 : 2x5 ; 2.54 mm(pitch) 3vcc msled ms1 ms1 note 4: (2)modified pull-down resistor tied to sd1 from 200k ohm to 1m ohm. scpsnt ms4 ms4 the trade marks and intellectual property rights of memory stick belong to sony corporation.information check: http://www.memorystick.org memory stick socket (1) circuit. (2)dma transaction cannot be supported in this version. pin 1 there is either function of sd and ms can be used on versio a but two sockets interface can be implemented on version b. scclk sdled scpsnt r2 33 1 2 (1)modified some erroneous netname like scpwr#,mspwr# and sdpwr#. note 6: w83l518d recommend circuit 0.6 b 22 wednesday, october 02, 2002 title size document number rev date: sheet of r11 1m 1 2 d2 led 2 jp2 1 2 3 4 5 6 7 8 9 10 (ver 0.3 --> ver 0.4) for the recommended reader, please contact to taiwan zetatronic industrial co.,ltd(http://www.tzt.com.tw) scio mspwctl# sd2 ms_3vcc sd2 sd3 r5 200k 1 2 <> ms4 ms5 c1 0.1u 1 2 scled (ver 0.4 --> ver 0.5) msled ms1 ms3 pin 10 scc4 scc8 q2 npn sdclk j1 ms_socket 1 2 3 4 5 6 7 8 9 10 soft start to protect mosfet(optional) pin 10 ms_3vcc 3vcc 3vcc (1)modified sd2,3,4,5 pull up to sd_3vcc. pin 1 msled note 7: + c2 1u ms3 sdpwctl# c3 0.1u (option:reserved for power-down) sd4 pin 1 there are some difference as following from previous version: ms2 (2)add without sd led recommend circuit.
w83l518d publication release date: may 17, 2005 - 23 - revision 1.0 11. revision history version date page description 1.0 02/jul. 1 st release 1.1 02/sep. recommend circuit modification. 1.11 02/oct. recommend circuit modification. 1.12 03/nov. the functions modification. (page 2) a1 may 17, 2005 23 add important notice important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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